The present invention is related to field-effect transistor devices for electrical signal control and switching, particularly analog signals, and more particularly, to the geometry and other material proper ties of the field-effect transistor device design for a field-effect transistor device analog signal switch.
The field-effect transistor has certain attributes which are attractive for analog signal switching. The first of these is that a field-effect transistor can be a bilateral device so that, for AC signal switching, the field-effect transistor appears to have the same output characteristics whatever the voltage polarities are at which the designated source and drain regions in the device happened to be operated at during any point in an AC voltage cycle. Further, there is no offset voltage in the source-drain volt-ampere characteristics of a common source operated field-effect transistor as there is in the collector voltmapere characteristic of a common emitter operated bipolar transistor.
A problem with the field-effect transistor for use as an analog signal switch exists, however, in that the "on" condition resistance between the drain and source of the field-effect transistor is typically quite a bit higher than that experienced, for instance, in the output of a bipolar transistor. Such an "on" condition drain-to-source resistance, or channel resistance, has deleterious effects on switching operations. First, this resistance increases the power dissipation occurring in the switch when in the "on" condition, a situation which is particularly troublesome if the field-effect transistor device is to be used as a power device carrying substantial currents in the "on" condition. Secondly, this "on" condition resistance slows the switching speed of the field-effect transistor-load combination limiting the usefulness of the switch for controlling rapidly changing analog signals.
For field-effect transistors formed in a semiconductor body, such as in FIG. 1A, the "on" condition drain-to-source resistance has been found to depend upon various material parameters of the materials used in the construction thereof, and upon the dimensions thereof; in the latter instance, particularly, upon the effective width and length of the field-effect transistor device in the semiconductor material used. That is, the "on" condition channel resistance is dependent upon the effective length of the channel between the sources and drains therein, and upon the effective width of the channel between sources and drains therein facing one another across the channel. The following relationship has been found: EQU R.sub.on .varies. L/w.
As is also known, the "punch-through" voltage and the device switching time device parameters are each determined substantially by the channel length, L, with both decreasing with decreasing L. Thus, one might conclude that channel length L in the stripe geometry transistor of FIG. 1A should be made as small as practically possible while increasing the channel width, w, to the extent necessary to achieve a satisfactorily small R.sub.on. That is, one might keep the channel length as short as possible, consistent with the design layout rules required by the fabrication process and with the need to maintain an adequate punch-through voltage minimum for operation in the "off" condition, and then extend the channel width until a satisfactory "on" condition drain-to-source resistance is achieved. The result of this design criteria is suggested in FIG. 1B.
In FIGS. 1A and 1B, the source region, 10, is formed beneath, but intersecting, a planar major surface of a semiconductor material body, this surface supporting an insulating layer thereover. The source region is also marked by S. A cut or opening, 11, in the insulating layer is shown to accommodate an electrical contact to source 10, and this contact is shown made by an external interconnection means, 12, in FIG. 1A. There need not be an external connector, however, as source region 10 may be extended to other regions in the semiconductor material body to thereby provide its own interconnection. No such external interconnection is shown in FIG. 1B where source 10 is indicated to extend indefinitely until some value of w is reached which provides a suitably small "on" condition channel resistance. Again, however, between solid lines, region 11 is shown in FIG. 1B to accommodate an external interconnection means.
A drain region, 13, is shown in FIGS. 1A and 1B and marked with a D. Again, a cut or opening, 14, is shown for providing a connection to source 13 via this opening by an external interconnection means, 15, by way of example. In FIG. 1B, again the drain region 13 shown to extend indefinitely until a satisfactory w dimension is reached to provide a sufficiently small R.sub.on.
FIGS. 1A and 1B each have a gate structure, 16, between source region 10 and drain region 13. Structure 16 may either be a gate conductor for a MOSFET, separated therefrom by an insulating layer, or structure 16 may be part of an interconnection means for electrically connecting to the gate region provided in a JFET.
Thus, FIG. 1B represents a possible method for increasing the channel width w to the extent necessary to reduce the "on" condition channel resistance. However, the efficacy of such a structure must be questioned for use as an analog signal switch because the long gate leads, and perhaps the source and drain leads, introduce added resistance which has a negative effect on the switching time and which increases power dissipation. Further, such a structure will take up area in a major surface when formed in a monolithic integrated circuit with no indication that the area is being consumed optimally.
Using up such area in a major surface of a monolithic integrated circuit is an expensive proposition. Experience has shown that the yield of operable integrated circuit chips from the fabrication process for a given monolithic integrated circuit is inversely proporational to the area of the major surface taken up by that monolithic integrated circuit. The cost, then, for a good monolithic integrated circuit chip is inversely proportional to the number of such chips formed in a wafer times the yield, with the result that the cost becomes proportional to the square of the area taken up in the major surface of the monolithic integrated circuit chip.
Thus, when considering the production of a monolithic integrated circuit chip, there is an extreme importance attached to the minimizing of the area of the major surface required therein. For field-effect transistor devices fabricated at a major surface of a monolithic integrated circuit, the minimization of the area of this major surface devoted to such field-effect transistor devices, for a given "on" channel resistance, is equivalent to minimization of the "on" condition channel resistance-device area product (R.sub.on A). This is because the R.sub.on A product ultimately determines the size of the monolithic integrated circuit chip major surface required to accommodate such field-effect transistor devices. Minimizing the field-effect device surface area used for a given "on" condition channel resistance also serves to minimize the gate area over the channel region, which improves switching speed by reducing both gate means resistance and the capacitances associated therewith.
FIG. 1C shows an alternative way to effectively increase the channel width while maintaining the channel length as small as possible. That is, rather than having a single long source, a single long drain, and a single long gate, there are provided multiple sources, drains, and gates repeated in a stripe effect pattern. This essentially represents dividing the structure of FIG. 1B several times and placing the resulting portions side by side.
Another geometrical layout which seeks to further reduce the R.sub.on A product beyond that reduction achieved by the structure of FIG. 1C is shown in U.S. Pat. No. 3,783,349 to Beasom. The Beasom reference discloses arranging rectangular or square source and drain regions in a semiconductor material body, separated by surfaces in the body major surface associated with gate portions, to form a grid or rectangular mesh arrangement having the sources and drain regions along intersections or centers of a grid pattern formed by sets of perpendicular lines. A portion of the essence of the pattern in the Beasom reference is repeated in FIG. 2 herein.
Source regions intersecting the surface of the semiconductor material body in FIG. 2 are again marked with S and by the numeral 10. The drain regions on the semiconductor material body are again marked with D and by the numeral 13. The portions of FIG. 2 associated with the gate regions are again marked with the letter G and by the numeral 16. Once again, the device of FIG. 2 is assumed to have an insulating layer over a semiconductor material body leading to the source and drain regions being shown in dashed lines. No interconnection means for the sources and drains are shown. Those portions of the source and drain regions which electrical contact would be made are shown by the solid line openings which are again marked by the numerals 11 and 14.
A further design geometry for this purpose is shown in U.S. Pat. No. 4,015,278 to Fukuta. In this situation, the sources are shown in the geometrical form of a letter "Y" while the drains are shown in geometrical form of a hexagon.
These alternative geometrical designs for field-effect transistors do indeed appear to aide in reducing the R.sub.on A product from the initially shown geometrical design layouts of FIGS. 1A and 1B for the various layout criteria. However, further improvements in the reduction of the R.sub.on A product are most desireable, especially where the field-effect transistor device is to be formed in a monolithic integrated circuit and be capable of controlling substantial currents therethrough without overheating the monolithic integrated circuit chip.